`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:28:48 07/06/2012
// Design Name:   IPv4ArpCache
// Module Name:   /home/azonenberg/native/programming/achd-soc/trunk/hdl/achd-soc/testIPv4ArpCache.v
// Project Name:  achd-soc
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: IPv4ArpCache
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module testIPv4ArpCache;

	// Inputs
	reg clk = 0;
	reg [31:0] ip_addr = 0;
	reg [47:0] mac_in = 0;
	reg wr = 0;

	// Outputs
	wire [47:0] mac_out;
	wire cache_hit;

	// Instantiate the Unit Under Test (UUT)
	IPv4ArpCache uut (
		.clk(clk), 
		.ip_addr(ip_addr), 
		.mac_in(mac_in), 
		.wr(wr), 
		.mac_out(mac_out), 
		.cache_hit(cache_hit)
	);

	reg ready = 0;
	initial begin
		#100;
		ready = 1;
	end
	
	always begin
		#5;
		clk = ready;
		#5;
		clk = 0;
	end
	
	reg[15:0] state = 0;
	always @(posedge clk) begin
		
		ip_addr <= 0;
		mac_in <= 0;
		wr <= 0;
		
		case(state)
			
			//Look for 192.168.1.1 (should be a miss)
			0: begin
				$display("Looking for 192.168.1.1 (expecting a miss)...");
				ip_addr <= {8'd192, 8'd168, 8'd1, 8'd1};
				state <= 1;
			end
			1: begin
				if(cache_hit)
					$display("    FAIL - got a hit, expected a miss");
				else
					$display("    PASS");
				state <= 2;
			end
			
			//Write 192.168.1.1 with mac address 00:de:ad:be:ef:00
			2: begin
				ip_addr <= {8'd192, 8'd168, 8'd1, 8'd1};
				mac_in <= 48'h00deadbeef00;
				wr <= 1;
				state <= 3; 
			end
			
			//Read it back and verify it was a hit
			3: begin
				ip_addr <= {8'd192, 8'd168, 8'd1, 8'd1};
				state <= 4;
			end
			4: begin
				state <= 5;
			end
			5: begin
				if(!cache_hit || (mac_out != 48'h00deadbeef00) )
					$display("    FAIL - got a miss or bad data");
				else
					$display("    PASS");
				state <= 6;
			end
			
		endcase
		
	end
      
endmodule

